1. Field of the Invention
The present invention relates to a method of forming a contact hole of a semiconductor device. More particularly, the present invention relates to a method of forming a contact hole of a semiconductor device that is able to reduce a generation of a defect due to an overetching of an interlayer dielectric layer during a cleaning process after the formation of the contact hole.
2. Description of the Related Art
Recently, the design of semiconductor devices has made rapid progress as information media, such as computers, become widely used. In particular, this progress has required semiconductor devices to function at a high operating speed and to have a large storage capacitance. In order to satisfy these requirements, semiconductor devices with increased density, reliability, and response time are under development. To increase an integration degree, a cell size should be reduced, and according to the reduction of the cell size, the size and margin of all types of patterns formed on a semiconductor substrate should similarly be reduced. On the other hand, the aspect ratio of each component comprising the semiconductor device gradually increases.
A polysilicon gate structure having a good electric characteristic, reliability and integration degree has been adopted as a driving device since the initial very large scale integration (VLSI). Therefore, the polysilicon gate structure has been largely advanced in an industrial field, such as a large scale integration (LSI) for a micro-computer or a device of a high-density memory, and is widely used in various fields today. Since the melting point of polysilicon is high, a self-align method can be applied during formation of a gate electrode along with a diffusion region of source and drain when using polysilicon. In addition, after patterning the gate electrode using polysilicon, a thermal oxidation of polysilicon also can be applied. Accordingly, damage generated at an edge portion of the gate electrode due to a reactive ion etching can be compensated. In addition, when an electric voltage is applied to the gate electrode, a high fringe electric field at the edge portion of the gate electrode is lowered to increase reliability of the semiconductor device.
However, for minute devices having a design rule of about 1 μm or less, an effect of increasing an operating speed of the devices through the increasing of the integration degree is not obtainable for a polysilicon gate structure. In addition, an increase in a wiring resistance through a reduction of the design rule and an increase in a signal transfer delay through the reduction of the wiring pitch and the increase in the capacitance, become significant issues. Further, a device frequency characteristic is deteriorated because the polysilicon gate structure has a relatively high resistance as compared to other conductive materials.
Accordingly, silicide compounds having similar characteristics with polysilicon while having a resistance ten times lower than polysilicon and having a high melting point are applied as a new material for forming a gate electrode. Typically, tungsten silicide is used as the silicide compound.
In addition, the design rule of recently developed and highly integrated semiconductor devices has been reduced to about 0.15 μm or less. In accordance with the reduction of the design rule, the size of a contact hole that is an electrically contacting portion to silicon is gradually reduced. A buried contact (BC) processing margin for an electrical contact of a storage node with a source/drain region of a transistor also is largely limited. Accordingly, a self-align method is widely used in order to confirm the BC processing margin. In addition, a spacer is formed on the sidewall portion of the gate electrode to prevent a contact between the storage node and the gate electrode. However, as the design rule is gradually reduced, the confirmation of the BC processing margin becomes problematic.
A conventional method of forming a contact hole of a semiconductor device by the self-align method will now be described with reference to the attached drawings in detail below.
FIGS. 1A to 1E illustrate cross-sectional views of stages in a conventional method of forming a contact hole of a semiconductor device according to the prior art. The following is an example of a BC processing.
Referring to FIG. 1A, a first oxide layer 120 is formed on an active region of a semiconductor substrate 100, such as a silicon substrate, using a thermal oxidation method. The semiconductor substrate 100 is divided into an active region and a field region by a field oxide layer 110 having a thickness of about 1800-2000 Å. Next, a conductive layer 130 and a capping insulation layer 140 are sequentially formed on the semiconductor substrate 100, on which the first oxide layer 120 is formed. The conductive layer 130 is either a doped polysilicon layer or a polycide layer. As the conductive layer 130, the polycide layer includes a doped polysilicon layer having a thickness of about 800-1200 Å and a refractory metal silicide layer having a thickness of about 1300-1700 Å. As the refractory metal silicide layer, a tungsten silicide (WSix) layer, a tantalum silicide (TaSi2) layer, a titanium suicide (TiSi2) layer, a cobalt silicide (CoSi2) layer, a molybdenum silicide (MoSi2) layer, or the like are widely applied.
The capping insulation layer 140 is preferably comprised of silicon nitride, which has a high etching selectivity with respect to an oxide layer. As the capping insulation layer 140, the silicon nitride layer is formed by depositing a nitride compound such as silicon nitride (SiN) to a thickness of about 800-1200 Å by means of a plasma enhanced chemical vapor deposition method (PE-CVD). The capping insulation layer 140 functions to protect the conductive layer 130 during the performance of subsequent etching and ion implantation processes.
A second oxide layer 150 is formed on the capping insulation layer 140. The second oxide layer 150 is formed by depositing a hot temperature oxide (HTO), such as silicon oxide, to a thickness of about 800-1200 Å by means of a low pressure chemical vapor deposition method (LPCVD). The second oxide layer 150 functions as an etch stop during the subsequent performance of an etching process for forming a spacer.
Referring to FIG. 1B, photoresist is coated on the second oxide layer 150 to form a photoresist layer. Next, a photoresist pattern (not shown) for forming a gate electrode is formed by photolithography. Then, the second oxide layer 150, the capping insulation layer 140, the conductive layer 130 and the first oxide layer 120 are continuously patterned using the photoresist pattern as an etching mask to form parallel gate patterns 160 having a gap therebetween on a predetermined region of the substrate. Each of the gate patterns 160 includes a subsequently integrated first oxide layer pattern 121, conductive layer pattern 131, capping insulation layer pattern 141 and second oxide layer pattern 151. The gate patterns 160 correspond to gate electrodes.
Referring to FIG. 1C, silicon nitride is deposited on the entire surface of the semiconductor substrate 100, on which the gate pattern 160 is formed, to form silicon nitride layer (not shown) as an insulation layer to a thickness of about 1200 Å. Then, an etch-back process is carried out until an active region of the semiconductor substrate 100 is exposed thereby forming a spacer 170 on a sidewall portion of the gate pattern 160.
During the etching to form the spacer 170, a surface portion of the semiconductor substrate is damaged. To cure the etching damage, a thermal oxidation is performed at a predetermined temperature. At this time, a thin thermal oxide layer grows between the gate patterns 160 and on the surface of the semiconductor substrate 100. The thermal oxidation layer that is formed is called a MTO (medium temperature oxide).
An ion implantation process is then performed to form a source/drain region (not shown) between gate patterns 160 and onto the semiconductor substrate 100 using the thin thermal oxide layer as a screen oxide layer. In order to perform the ion implantation, a region is masked to implant appropriate impurities into a desired region. Then, the impurities are implanted into the active region of the exposed semiconductor substrate 100 and a diffusion region of the source/drain of a transistor is formed. During the ion implantation, the gate electrode 160 and the spacer 170 formed at the sidewall portion of the gate electrode 160 function as the mask.
Referring to FIG. 1D, an interlayer dielectric 180 is formed on the semiconductor substrate 100 on which the gate electrode 160 and the spacer 170 are formed. The interlayer dielectric 180 is formed by depositing materials having a good gap filling characteristic, such as silicon oxide, borophosphorous silicate glass (BPSG), phosphorous silicate glass (PSG), high density plasma (HDP) oxide, tetraethyl ortho silicate (TEOS), or the like by an LPCVD method or a PE-CVD method and then, planarizing the deposited material by a planarizing method such as a chemical mechanical polishing (CMP). Next, a photoresist pattern 191 having a predetermined shape for patterning the interlayer dielectric and to form a contact hole is formed.
Referring to FIG. 1E, the interlayer dielectric 180 is etched using the photoresist pattern 191 as an etching mask to form an interlayer dielectric pattern 181, while exposing the substrate between the gate patterns 160. That is, the source/drain region between the gate patterns 160 is exposed to form a self-aligned contact hole 200. The etching of the interlayer dielectric is performed using a mixed gas including a gas having a high carbon/fluorine ratio, such as C3F8, C4F8, CO, or the like and by using an etching apparatus having a high ionization degree.
Then, a conductive material is deposited on the substrate 100, on which the interlayer dielectric pattern 181 including the contact hole 200 are formed, to form a contact or a storage node (not shown).
After completing the formation of the contact hole by the anisotropic etching, a cleaning process is performed so that a subsequently deposited conductive material is able to form an ohmic contact with the substrate. This cleaning process is carried out to remove contaminants present on the substrate such as organic materials, particles, and the like and to remove a native oxide formed on the substrate. The native oxide is an oxide layer naturally formed during the exposure of the substrate to the atmosphere.
As the integration degree of the semiconductor devices increases and as the design rule decreases, the interlayer dielectric is required to have greater gap filling characteristics. In addition, the margin required for accomplishing an insulated state between the patterns is gradually reduced. Generally, BPSG is used for the formation of the interlayer dielectric after forming the gate. When forming the self-aligned contact (SAC) for connecting DC (direct contact) and BC (buried contact), the distance between adjacent contact holes is too narrow and a cleaning is not sufficiently performed before the deposition of a conductive material, such as polysilicon, for forming a pad. During cleaning, the interlayer dielectric as well as the impurities are also etched by a cleaning solution. When the concentration of boron and phosphorus is high in the BPSG (borophosphorous silicate glass), a high reflowing property is obtained and the gap filling characteristic is improved. However, since the etching characteristic of the cleaning solution is also improved, the concentration of boron and phosphorus is not able to be sufficiently increased.
As a result, the size of the interlayer dielectric pattern represented by distance “a” in FIG. 1E decreases, and the interlayer dielectric pattern might be lost by overetching of the interlayer dielectric layer pattern during cleaning, thereby subsequently generating a bridge. Accordingly, a sufficient cleaning is not able to be performed in view of the above-described problem and so a defect, such as a single bit failure, may be created.
For cleaning a contact hole during the manufacture of a semiconductor device, various methods of removing organic materials and inorganic materials, such as metallic residues including a native oxide layer, an oxide layer, contaminants, and the like are combined. Atypical conventional cleaning method winnow be described.
First, the substrate is cleaned using piranha, which is a sulfuric acid solution obtained by mixing sulfuric acid and hydrogen peroxide or standard cleaning solution-1 (SC-1), which is an ammonia solution obtained by mixing aqueous ammonia, hydrogen peroxide and pure water. Through this cleaning, particles and organic materials are removed. Then, the substrate is rinsed using a quick dump rinse (QDR) method.
Second, the substrate is cleaned using a hydrogen fluoride-containing solution or a buffered oxide etching (BOE) solution to remove the oxide layer and then rinsed using de-ionized water and by applying an over-flowing method.
Third, the substrate is cleaned using a hydrochloric acid solution obtained by mixing hydrochloric acid, hydrogen peroxide and pure water, to remove inorganic materials. Recently, this third step of the cleaning may be omitted in some instances as the purity of the chemicals used has improved. After completing the cleaning, the substrate is dried using a dryer.
Disadvantageously, a large amount of chemicals are consumed in the conventional cleaning process as described above and the cleaning requires a long time. In addition, as the size of a wafer increases, the size of the cleaning apparatus must also increase, which then occupies a large area within a cleaning room, thereby lowering productivity.
Further, according to the conventional cleaning method of the contact hole, a native oxide layer grows in the chemical material to a thickness of about 10 Å because the organic and inorganic material present on the surface of the contact hole is removed using a sulfuric acid solution at a high temperature of about 130° C. Therefore, the performance time for the cleaning process to remove the native oxide through dipping into the hydrogen fluoride solution or BOE solution should be increased. As a result of this increase in dipping time, the loss of the interlayer dielectric layer pattern formed as the sidewalls of the contact hole becomes severe.
An electric insulation might be broken between a first polysilicon layer for a gate electrode and a second polysilicon layer for a bit line, between a first polysilicon layer for a gate electrode and a third polysilicon layer for a storage node, and between a second polysilicon layer for a bit line and a third polysilicon layer for a storage electrode, thereby deteriorating device characteristics.
Recently, after removing the organic and inorganic material, a diluted HF (DHF) solution has been widely used to completely remove the native oxide layer in a short time and to minimize the loss of the sidewall forming the contact hole. The DHF solution is a cleaning solution obtained by mixing water and hydrogen fluoride in a mixing ratio of about 200:1 by volume. The DHF solution is effective for removing the native oxide formed on a bottom portion of the contact hole and particles present in the contact hole. However, since the DHF solution also has a high etching selectivity with respect to BPSG, an application of a DHF solution in the manufacture of a minute device is not advantageous.
FIG. 2 is a graph illustrating an etching amount (i.e., an etched amount) of SiN and BPSG and an etching ratio between SiN and BPSG during the performance of a cleaning process using a DHF solution after the formation of a contact hole. Line a represents an etched amount of SiN, line c represents an etched amount of BPSG and line b represents an etching ratio of BPSG/SiN.
Referring to FIG. 2, the etching amounts of both SiN and BPSG increase when cleaning time increases. However, the etching amount of BPSG increases at an even higher ratio than SiN. Further, when comparing the etching amount of BPSG with SiN, BPSG is etched faster than SiN by about 21.3-26.7 times. Through this analysis, it may be determined that the BPSG forming the interlayer dielectric is excessively etched by a hydrogen fluoride cleaning solution.